Stephen Brink

Member for

2 years 2 months
First Name
Stephen
Last Name
Brink
Studying for
Research Interests

integrated circuit design, neural computation, neuromorphic engineering, analog signal processing, floating-gate transistor arrays

Biography

Stephen grew up in Arizona and studied bioengineering at Arizona State University before coming to Georgia Tech.

Thesis Project Title
Learning in silicon: a floating-gate based, biophysically inspired neuromorphic hardware system with synaptic plasticity
Thesis Project Description

The basic goal of neuromorphic engineering is to create electronic systems that behave like neural systems in biology. Such systems will be useful tools for neural interfacing, for biologically inspired signal processing, and for the neuroscience community's search for fundamental understanding of neural information processing. The investigator will present the first neuromorphic hardware system to allow spiking network simulation using biophysically inspired neuron models and floating-gate based single transistor learning synapses (STLS). These architectural features allow good biological fidelity and silicon area efficiency, which will enable an aggressive roadmap for scaling the neuromorphic system's ability to model larger neural systems. The specific aims of the proposed work are threefold. The first aim is to use the above neuromorphic system to perform network simulations of several network architectures that have well-understood computational properties. These simulations will be done without synaptic plasticity in order to gain an understanding of the electrophysiological fidelity of the system at a network level. The second aim is to study the role of synaptic plasticity in those same architectures, and to assess the ways in which the computation performed by the networks is improved by this learning process. The third aim is to perform an experimental study of floating-gate transistor adaptation outside the context of a spiking network in order to gain insight into principles for design of floating-gate based adaptation in both neuromorphic systems and other computational analog hardware.

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